ST90135 datasheet(177/190 Pages) STMICROELECTRONICS

177 / 190 page

177/190

ST90158 - ELECTRICAL CHARACTERISTICS

EXTERNAL BUS TIMING TABLE

(VDD =5V ± 10%, TA = -40°C+ 85°C, Cload = 50pF, INTCLK = 16MHz, unless otherwise specified)

Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,

prescale value and number of wait cycles inserted.

The values in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler

value of zero and zero wait status.

Legend:

Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;

2*OSCIN period when OSCIN is divided by 2;

OSCIN period / PLL factor when the PLL is enabled

TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)

TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)

P = clock prescaling value (=PRS; division factor = 1+P)

Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)

Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)

Symbol

Parameter

Value (Note)

Unit

Formula

Min. Max.

TsA (AS)

Address Set-up Time before AS

↑

Tck*Wa+TckH-9

ThAS (A)

Address Hold Time after AS

↑

TckL-4

TdAS (DR)

↑ to Data Available (read)

Tck*(Wd+1)+3

TwAS

AS Low Pulse Width

Tck*Wa+TckH-5

TdAz (DS)

Address Float to DS

↓

TwDS

DS Low Pulse Width

Tck*Wd+TckH-5

TdDSR (DR)

↓ to Data Valid Delay (read)

Tck*Wd+TckH+4

ThDR (DS)

Data to DS

↑ Hold Time (read)

TdDS (A)

↑ to Address Active Delay

TckL+11

TdDS (AS)

↑ to AS ↓ Delay

TckL-4

TsR/W (AS)

R/W Set-up Time before AS

↑

Tck*Wa+TckH-17

TdDSR (R/W)

↑ to R/W and Address Not Valid Delay

TckL-1

TdDW (DSW)

Write Data Valid to DS

↓ Delay

-16

TsD(DSW)

Write Data Set-up before DS

↑

Tck*Wd+TckH-16

ThDS (DW)

Data Hold Time after DS

↑ (write)

TckL-3

TdA (DR)

Address Valid to Data Valid Delay (read)

Tck*(Wa+Wd+1)+TckH-7

TdAs (DS)

↑ to DS ↓ Delay

TckL-6

ST90135 Datasheet(PDF) 177 Page - STMicroelectronics

ST90135 Datasheet(HTML) 177 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL