TAS5705PAPRG4 datasheet(46/71 Pages) TI

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TAS5705

SLOS549 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com

Table 7. Serial Control Interface Register Summary (continued)

NO. OF

INITIALIZATION

SUBADDRESS

CONTENTS

BYTES

VALUE

0x12

IC delay channel 2

Description shown in subsequent section

0x34

0x13

IC delay channel 3

Description shown in subsequent section

0x1C

0x14

IC delay channel 4

Description shown in subsequent section

0x64

0x15

IC delay channel 5

Description shown in subsequent section

0xB0

0x16

IC delay channel 6

Description shown in subsequent section

0x90

0x17

Offset register

Reserved

0x00

0x18

Reserved(2)

0x19

PWM shutdown group

0x30

0x1A

Start/stop period register

0x0A

0x1B

Oscillator trim register

0x82

0x1C

BKND_ERR register

0x02

0x1D–0x1F

Reserved(2)

0x20

Input Mux register

Description shown in subsequent section

0x0089 777A

0x21

Downmix input Mux register

Description shown in subsequent section

0x0000 4203

0x22

AM tuned frequency

Description shown in subsequent section

0x0000 0000

0x23

ch6_bq[2] (Loudness BQ)

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x24

ch6_bq[3] (post volume

u[31:26], b0[25:0]

0x0080 0000

BQ)

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x25

PWM Mux register

Description shown in subsequent section

0x0102 1345

0x26

1/G register

u[31:26], x[25:0]

0x0080 0000

0x27

Reserved(3)

0x28

Scale register

u[31:26], x[25:0]

0x0080 0000

0x29

ch1_bq[0]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x2A

ch1_bq[1]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x2B

ch1_bq[2]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

(3)

Reserved registers should not be accessed.

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