TMS320DM335 datasheet(20/156 Pages) TI

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2.4.4

DDR Memory Interface

TMS320DM335

Digital Media System-on-Chip (DMSoC)

SPRS528 – JULY 2008

www.ti.com

Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)

TERMINAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

Async EMIF: Lowest numbered chip select. Can be programmed to be used for

EM_CE0/

standard asynchronous memories (example: flash), OneNAND, or NAND

J16

I/O/Z

VDD

GIO037

memory. Used for the default boot and ROM boot modes.

GIO: GIO[037]

Async EMIF: Second chip select. Can be programmed to be used for standard

EM_CE1/

G19

I/O/Z

VDD

asynchronous memories(example: flash), OneNAND, or NAND memory.

GIO036

GIO: GIO[036]

Async EMIF: Write Enable

EM_WE/

J15

I/O/Z

VDD

NAND/SM/xD: WE (Write Enable) output

GIO035

GIO: GIO[035]

Async EMIF: Output Enable

EM_OE/

F19

I/O/Z

VDD

NAND/SM/xD: RE (Read Enable) output

GIO034

GIO: GIO[034]

Async EMIF: Async WAIT

EM_WAIT/

G18

I/O/Z

VDD

NAND/SM/xD: RDY/ BSY input

GIO033

GIO: GIO[033]

EM_ADV/

OneNAND: Address valid detect for OneNAND interface

H16

I/O/Z

VDD

GIO032

GIO: GIO[032]

EM_CLK/

OneNAND: Clock for OneNAND flash interface

E19

I/O/Z

VDD

GIO031

GIO: GIO[031]

The DDR EMIF supports DDR2 and mobile DDR.

Table 2-10. DDR Terminal Functions

TERMINAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

DDR_CLK

I/O/Z

VDD_DDR

DDR Data Clock

DDR_CLK

I/O/Z

VDD_DDR

DDR Complementary Data Clock

DDR_RAS

I/O/Z

VDD_DDR

DDR Row Address Strobe

DDR_CAS

I/O/Z

VDD_DDR

DDR Column Address Strobe

DDR_WE

W10

I/O/Z

VDD_DDR

DDR Write Enable

DDR_CS

I/O/Z

VDD_DDR

DDR Chip Select

DDR_CKE

V10

I/O/Z

VDD_DDR

DDR Clock Enable

DDR_DQM[1]

U15

I/O/Z

VDD_DDR

Data mask outputs:

•

DDR_DQM[1] - For DDR_DQ[15:8]

DDR_DQM[0]

T12

I/O/Z

VDD_DDR

•

DDR_DQM[0] - For DDR_DQ[7:0]

DDR_DQS[1]

V15

I/O/Z

VDD_DDR

Data strobe input/outputs for each byte of the 16-bit data bus used to

synchronize the data transfers. Output to DDR when writing and inputs when

reading.

DDR_DQS[0]

V12

I/O/Z

VDD_DDR

•

DDR_DQS[1] - For DDR_DQ[15:8]

•

DDR_DQS[0] - For DDR_DQ[7:0]

DDR_BA[2]

I/O/Z

VDD_DDR

Bank select outputs. Two are required for 1Gb DDR2 memories.

DDR_BA[1]

I/O/Z

VDD_DDR

Bank select outputs. Two are required for 1Gb DDR2 memories.

DDR_BA[0]

I/O/Z

VDD_DDR

Bank select outputs. Two are required for 1Gb DDR2 memories.

DDR_A13

I/O/Z

VDD_DDR

DDR Address Bus bit 13

DDR_A12

I/O/Z

VDD_DDR

DDR Address Bus bit 12

DDR_A11

I/O/Z

VDD_DDR

DDR Address Bus bit 11

DDR_A10

I/O/Z

VDD_DDR

DDR Address Bus bit 10

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2)

Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.

(3)

PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k

Ω resistor should be used.)

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