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AD9388ABSTZ-5P Datasheet(PDF) 12 Page - Analog Devices |
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AD9388ABSTZ-5P Datasheet(HTML) 12 Page - Analog Devices |
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12 / 28 page ![]() AD9388A Rev. B | Page 12 of 28 Pin No. Mnemonic Type1 Description 121 RXA_2N I Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2P I Digital Input Channel 2 True of Port A in the HDMI Interface. 128 RXB_CN I Digital Input Clock Complement of Port B in the HDMI Interface. 129 RXB_CP I Digital Input Clock True of Port B in the HDMI Interface. 131 RXB_0N I Digital Input Channel 0 Complement of Port B in the HDMI Interface. 132 RXB_0P I Digital Input Channel 0 True of Port B in the HDMI Interface. 134 RXB_1N I Digital Input Channel 1 Complement of Port B in the HDMI Interface. 135 RXB_1P I Digital Input Channel 1 True of Port B in the HDMI Interface. 137 RXB_2N I Digital Input Channel 2 Complement of Port B in the HDMI Interface. 138 RXB_2P I Digital Input Channel 2 True of Port B in the HDMI Interface. 106 DDCA_SDA I/O HDCP Slave Serial Data Port A. 1 DDCB_SDA I/O HDCP Slave Serial Data Port B. 105 DDCA_SCL I HDCP Slave Serial Clock Port A. 144 DDCB_SCL I HDCP Slave Serial Clock Port B. 2 SPDIF O SPDIF Digital Audio Output. 3 I2S0 O I2S Audio (Channel 1 and Channel 2). 4 I2S1 O I2S Audio (Channel 3 and Channel 4). 5 I2S2 O I2S Audio (Channel 5 and Channel 6). 6 I2S3 O I2S Audio (Channel 7, and Channel 8). 7 LRCLK O LRCLK, Data Output Clock for Left and Right Audio Channels. 8 SCLK O Audio Serial Clock Output. 9 MCLKOUT O Audio Master Clock Output. 10 EXT_CLAMP I External Clamp Signal. This is an optional mode of operation for the AD9388A. 48 EXT_CLK I Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the AD9388A. 124 RTERM I Sets Internal Termination Resistance. Connect this pin to TGND using a 500 Ω resistor. 1 G = ground, P = power, I = input, and O = output. |
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