ADN8102ACPZ-R7 datasheet(17/32 Pages) AD

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ADN8102

Rev. A | Page 17 of 32

EQUALIZATION SETTINGS

The ADN8102 receiver incorporates a multizero transfer function

continuous time equalizer that provides up to 22 dB of high

frequency boost at 1.875 GHz to compensate up to 30 meters

of CX4 cable or 40 inches of FR4 at 3.75 Gbps. The ADN8102

allows joint control of the equalizer transfer function of the

four equalizer channels in a single port through the I2C control

interface. Port A and Port B equalizer transfer functions are

controlled via Register 0x80 and Register 0xA0, respectively.

The equalizer transfer function allows independent control of

the boost in two different frequency ranges for optimal matching

with the loss shape of the user’s channel (for example, skin-effect

loss dominated or dielectric loss dominated). By default, the

equalizer control is simplified to two independent maps of basic

settings that provide nine settings, each optimized for CX4 cable

and FR4 to ease programming for typical channels. The default

state of the part selects the CX4 optimized equalization map for

the IN_A[3:0] channels that interface with the cable and the FR4

optimized equalization map for the IN_B[3:0] channels that

interface with the board. Full control of the equalizer is available via

the I2C control interface by writing register bit MODE[0] = 1 at

Address 0x0F. Table 6 summarizes the high frequency boost for

each of the basic control settings and the typical length of CX4

cable and FR4 trace that each setting compensates. Setting the

EQBY bit of the IN_A/IN_B configuration registers high sets

the equalization to 1.5 dB of boost, which compensates 0 meters

to 2 meters of CX4 or 0 inches to 10 inches of FR4.

Setting the LUT SELECT bit = 1 (Bit 1 in the IN_Ax/IN_Bx FR4

control registers) allows the default map selection (CX4 or FR4

optimized) to be overwritten via the LUT FR4/CX4 bit (Bit 0)

in the IN_Ax/IN_Bx FR4 control registers. Setting this bit high

selects the FR4 optimized map, and setting it low selects the CX4

optimized map. These settings are set on a per channel basis

(see Table 7 and Table 17).

The user can also specify the boost in the mid frequency and high

frequency ranges independently. This is done by writing to the

IN_A/IN_B EQ1 control and IN_A/IN_B EQ2 control registers for

the channel of interest. Each of these registers provides 32 settings

of boost, with IN_A/IN_B EQ1 control setting the mid-frequency

boost and IN_A/IN_B EQ2 control setting the high frequency

boost. The IN_A/IN_B EQx control registers are ordered such

that Bit 5 is a sign bit, and midlevel boost is centered on 0x00;

setting Bit 5 low and increasing the LSBs results in decreasing

boost, while setting Bit 5 high and increasing the LSBs results in

increasing boost. The EQ CTL SRC bit (Bit 6) in the IN_A/IN_B

EQ1 Control registers determines whether the equalization

control for the channel of interest is selected from the optimized

map or directly from the IN_A/IN_B EQx control registers (per

port). Setting this bit high selects equalization control directly

from the IN_A/IN_B EQx control registers, and setting it low

selects equalization control from the selected optimized map.

Table 6. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)

IN_Ax/IN_Bx

Configuration, EQ[2:0]

Cable Optimized

FR4 Optimized

Boost (dB)

Typical CX4 Cable Length (Meters)

Boost (dB)

Typical FR4 Trace Length (Inches)

4 to 6

3.5

5 to 10

8 to 10

3.9

10 to 15

12 to 14

4.25

15 to 20

16 to 18

4.5

20 to 25

20 to 22

4.75

25 to 30

24 to 26

5.0

30 to 35

28 to 30

5.3

35 to 40

30 to 32

5.5

35 to 40

1 These EQ settings are also available via the external device pins, EQ_A[1:0] and EQ_B[1:0].

Table 7. Receive Configuration and Equalization Registers

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

IN_A/IN_B

Configuration

0x80, 0xA0

PNSWAP

EQBY

EQ[2]

EQ[1]

EQ[0]

0x30

IN_A/IN_B

EQ1 Control

0x83, 0xA3

EQ CTL SRC

EQ1[5]

EQ1[4]

EQ1[3]

EQ1[2]

EQ1[1]

EQ1[0]

0x00

IN_A/IN_B

EQ2 Control

0x84, 0xA4

EQ2[5]

EQ2[4]

EQ2[3]

EQ2[2]

EQ2[1]

EQ2[0]

0x00

IN_Ax/IN_Bx

FR4 Control

0x85, 0x8D, 0x95,

0x9D, 0xA5, 0xAD,

0xB5, 0xBD

LUT SELECT

LUT FR4/CX4

0x00

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