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ADN8102ACPZ-R7 Datasheet(PDF) 19 Page - Analog Devices |
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ADN8102ACPZ-R7 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 32 page  ADN8102 Rev. A | Page 19 of 32 LOOPBACK The ADN8102 provides loopback on both input ports (Port A: cable interface input, Port B: line card interface input). The external loopback toggle pin, LB, controls the loopback of the Port B input only (board side loopback). When loopback is asserted, valid data continues to pass through the Port B link, but the Port B input signals are also shunted to the Port A output to allow testing and debugging without disrupting valid data. This loopback, as well as loopback of the Port A input (cable side loopback), can be programmed through the I2C interface. The loopbacks are controlled through the I2C interface by writing to Bit 0 and Bit 1 of the global configuration control register (Register 0x02). Bit 1 represents loopback of the Port A inputs to the Port B outputs (cable side loopback). Bit 0 represents loopback of the Port B inputs to the Port A outputs (board side loopback), with high representing loopback for both bits. Bit 0 is also controlled through the LB pin with I2C data overwriting the pin state. Both input ports can be looped back simultaneously (full loopback) by writing high to both Bit 0 and Bit 1, but in this case, valid data is disrupted on each channel. Figure 39 illustrates the three loopback modes. CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CONTROL LOGIC TRANSMIT PRE-EMPHASIS RECEIVE EQUALIZATION EQ Ix_B[3:0] LB ADDR[1:0] SCL SDA RESET Ox_B[3:0] LOS_A Ix_A[3:0] PE_A[1:0] EQ_A[1:0] EQ_B[1:0] PE_B[1:0] ENA ENB RECEIVE EQUALIZATION EQ TRANSMIT PRE-EMPHASIS PE PE Ox_A[3:0] CABLE SIDE LOOPBACK BOARD SIDE LOOPBACK FULL LOOPBACK Figure 39. Loopback Modes of Operation Table 10. Global Configuration Register, Loopback Controls Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Global Configuration Control 0x02 LB[1] LB[0] 0x00 |
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