AT87C5103-ICSAL datasheet(8/64 Pages) ATMEL

8 / 64 page

4134B–8051–06/03

Registers

Table 1. CKCON0 Register

CKCON0 (S:8Fh)

Clock Control Register

Note:

1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = XX0X X000b

7654

3210

PCAX2

T1X2

T0X2

Bit

Number

Bit

Mnemonic

Description

–

Reserved

The value read from this bit is indeterminate. Do not set this bit.

–

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5PCAX2

Programmable Counter Array clock

(1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

–

Reserved

The value read from this bit is indeterminate. Do not set this bit.

–

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2T1X2

Timer1 Clock

(1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

1T0X2

Timer0 Clock

(1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

0X2

CPU Clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

the peripherals.

Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the

individual peripherals "X2" bits.

AT87C5103-ICSAL Datasheet(PDF) 8 Page - ATMEL Corporation

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