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AT87C5103-ICSAL Datasheet(PDF) 49 Page - ATMEL Corporation |
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AT87C5103-ICSAL Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 64 page  49 4134B–8051–06/03 Table 32. IE1 Register IE1 (S:B1h) Interrupt Enable Register Reset Value = XXXX X0XXb No Bit addressable 7654 3210 ----- ESPI -- Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2ESPI SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. 1- Reserved The value read from this bit is indeterminate. Do not set this bit. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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