JS48F4400P0VB00 datasheet(99/99 Pages) NUMONYX

99 / 99 page

November 2007

Datasheet

Order Number: 306666-11

P30

Appendix F Ordering Information for SCSP Products

Note:

For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations.

Note:

* The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density.

Figure 47: Decoder for SCSP P30

Table 50: Valid Combinations for Dual- Die Products

64-Mbit

128-Mbit

256-Mbit

512-Mbit*

RD48F2000P0ZBQ0

RD48F3000P0ZBQ0

RD48F4000P0ZBQ0

RD48F4400P0VBQ0

RD48F2000P0ZTQ0

RD48F3000P0ZTQ0

RD48F4000P0ZTQ0

PF48F4400P0VBQ0

PF48F2000P0ZBQ0

PF48F3000P0ZBQ0

PF48F4000P0ZBQ0

RC48F4400P0VB00

PF48F2000P0ZTQ0

PF48F3000P0ZTQ0

PF48F4000P0ZTQ0

PC48F4400P0VB00

TE48F4400P0VB00

JS48F4400P0VB00

F 4 0

P 0 Z B

D 4

0 0

Group Designator

48F = Flash Memory only

Package Designator

RD = Intel® SCSP, leaded

P F = Intel® SCSP, lead-free

RC = 64-Ball Easy BGA, leaded

P C = 64-Ball Easy BGA, lead-free

TE = 56-Lead TSOP , leaded

JS = 56-Lead TSOP, lead-free

Flash Density

0 = No die

2 = 64-Mbit

3 = 128-M bit

4 = 256-M bit

Product Family

P = Intel StrataFlash® Em bedded M em ory

0 = No die

Device Details

0 = Original version of the product

(refer to the latest version of the

datasheet for details)

Ballout Designator

Q = QUAD+ ballout

0 = Discrete ballout

Parameter, Mux Configuration

B = Bottom Param eter, Non Mux

T = Top Param eter, Non M ux

I/O Voltage, CE# Configuration

Z = Individual Chip Enable(s)

V = Virtual Chip E nable(s)

VCC = 1.7 V – 2.0 V

VCCQ = 1.7 V – 3.6 V

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