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74ALVCH16373 Datasheet(PDF) 1 Page - STMicroelectronics |
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74ALVCH16373 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 11 page ![]() 1/11 February 2003 s 3.6V TOLERANT INPUTS AND OUTPUTS s HIGH SPEED : tPD = 3.6 ns (MAX.) at VCC =3.0 to 3.6V tPD = 4.5 ns (MAX.) at VCC =2.3 to 2.7V tPD = 6.5 ns (MAX.) at VCC = 1.65V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL = 24mA (MIN) at VCC =3.0V |IOH|= IOL = 18mA (MIN) at VCC =2.3V |IOH|= IOL =4mA (MIN) at VCC = 1.65V s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V s BUS HOLD PROVIDED ON DATA INPUTS s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 s LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74ALVCH16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE latches are bite controlled by two latch enable inputs (nLE) and two output enable inputs (OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.This device is designed to be used with 3 state memory address drivers, etc. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ALVCH16373 LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS ORDER CODES PACKAGE TUBE T & R TSSOP 74ALVCH16373TTR TSSOP PIN CONNECTION |
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