M74HC40103

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TYPICAL APPLICATIONS

PROGRAMMABLE DIVIDE-BY-N COUNTER

PARALLEL CARRY CASCADING

PROGRAMMABLE TIMER

Timing Chart when N = "3"

HC40103 ... 1/2 to 1/256 are dividable

* At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival.

Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly

The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above