LFEC10 datasheet(32/163 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-34. LatticeECP/EC Banks

LatticeECP/EC devices contain two types of sysI/O buffer pairs.

Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)

The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers

and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also

be conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot

socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid

operating levels and the device has been conﬁgured.

Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-

enced input buffer can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O.

Only the left and right banks have LVDS differential output drivers. See the IDK speciﬁcation for I/O leakage cur-

rent during power-up.

REF1(2)

GND

CCIO2

REF2(2)

REF1(3)

GND

CCIO3

REF2(3)

REF1(7)

GND

TOP

BOTTOM

CCIO7

REF2(7)

REF1(6)

GND

CCIO6

REF2(6)

Bank 5

Bank 4

Bank 0

Bank 1

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