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M62376GP Datasheet(PDF) 3 Page - Renesas Technology Corp |
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M62376GP Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 11 page ![]() M62376GP REJ03D0881-0300 Rev.3.00 Mar 25, 2008 Page 3 of 10 Block Diagram for Explanation of Terminals EN CLK S15 S14 S13 S12 S11 S10 S9S8S7S6S5S4S3S2S1S0 Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0 EN EN ......... ... ... ... ............ ............ ............ 21 22 19 20 23 1 12 15 16 17 18 4 5 EN CLK SI RESET A1 A4 ...... D11/A5 ............ D4/A12 D3 D2 D1 D0 SO (12) (8) [1110] [0000] [1111] [1101] (8) (4) (8) A12 A5 A4 A1 13 14 24 VDD VCC GND + − + − + − + − Shift register 8-bit latch 8-bit D/A converter 8-bit latch 8-bit D/A converter Power ON RESET 8-bit latch 8-bit D/A converter 8-bit latch 8-bit D/A converter 8-bit latch Level shift Level shift Level shift Level shift Decoder (12) Decoder (4) Clock control circuit 12 -bit latch (11010000) (A5-A12 Hi-Z) Latch Latch Absolute Maximum Ratings Item Symbol Ratings Unit Conditions Digital supply voltage VCC –0.3 to +7.0 V Analog supply (D/A converter upper reference voltage) VDD –0.3 to +7.0 V Input voltage VIN –0.3 to VCC + 0.3 V VCC supply side pin Output voltage Vout –0.3 to VCC + 0.3 V VCC supply side pin Input voltage VIN –0.3 to VDD + 0.3 V VDD supply side pin Output voltage Vout –0.3 to VDD + 0.3 V VDD supply side pin Power dissipation Pd 200 mW Operating temperature Topr –20 to +85 °C Storage temperature Tstg –40 to +125 °C |
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