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HD404339FS Datasheet(PDF) 75 Page - Renesas Technology Corp |
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HD404339FS Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 80 page  HD404339 Series 73 a. After V CC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of t RC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 3. Refer to figure 56. 4. Refer to figure 57. 5. Refer to figure 58. 6. Refer to figure 59. 7. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. 8. Applies to the HD4074339. Serial Interface Timing Characteristics (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, Ta = –20 to +75 °C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1— — t cyc Load shown in figure 61 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 61 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 61 1 Transmit clock rise time t SCKr SCK — — 80 ns Load shown in figure 61 1 Transmit clock fall time t SCKf SCK — — 80 ns Load shown in figure 61 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 61 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1 ——t cyc 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc 1 Transmit clock rise time t SCKr SCK — — 80 ns 1 Transmit clock fall time t SCKf SCK — — 80 ns 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 61 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 Note: 1. Refer to figure 60. |
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