STV6886 datasheet(23/43 Pages) STMICROELECTRONICS

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STV6886

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OPERATING DESCRIPTION

1 GENERAL CONSIDERATIONS

1.1 Power Supply

The typical values of the power supply voltages

VCC and VDD are 12 V and 5 V respectively. Opti-

mum operation is obtained for VCC between 10.8

and 13.2 V and VDD between 4.5 and 5.5 V.

In order to avoid erratic operation of the circuit dur-

ing the transient phase of VCC switching on, or off,

the value of VCC is monitored: if VCC is less than

7.5 V typ., the outputs of the circuit are inhibited.

Similarly, before VDD reaches 4 V, all the I

2C reg-

ister are reset to their default value (see I2CBus

Address Table).

In order to have very good power supply rejection,

the circuit is internally supplied by several voltage

references (typ. value: 8.2 V). Two of these volt-

age references are externally accessible, one for

the vertical and one for the horizontal part. They

can be used to bias external circuitry (if ILOAD is

less than 5 mA). It is necessary to filter the voltage

references by external capacitors connected to the

respective grounds, in order to minimize the noise

and consequently the “jitter” on vertical and hori-

zontal output signals.

1.2 I2C Control

STV6886 belongs to the I2C-controlled device

family. Instead of being controlled by DC voltages

on dedicated control pins, each adjustment can be

done via the I2C Interface.

The I2C bus is a serial bus with a clock and a data

input. The general function and the bus protocol

are specified in the Philips-bus data sheets.

The inputs (Data and Clock) are comparators with

a 2.2 V threshold at 5 V supply. Spikes of up to 50

ns are filtered by an integrator and the maximum

clock speed is limited to 400 kHz.

The data line (SDA) can receive or transmit data.

In read-mode the IC sends reply information

(1 byte) to the micro-processor.

The bus protocol prescribes a full-byte transmis-

sion in all cases. The first byte after the start con-

dition is used to transmit the IC-address (hexa 8C

for write, 8D for read).

1.3 Write Mode

In write mode the second byte is the subaddress of

the selected function to adjust (or controls to af-

fect) and the third byte the corresponding data

byte. It is possible to send more than one data byte

to the IC. If after the third byte no stop or start con-

dition is detected, the circuit increments automati-

cally by one the momentary subaddress in the

subaddress counter (auto-increment mode). So it

is possible to transmit immediately the following

data bytes without sending the IC address or sub-

address. This can be useful to reinitialize all the

controls very quickly (flash manner). This proce-

dure can be finished by a stop condition.

The circuit has 18 adjustment capabilities: 3 for the

horizontal part, 4 for the vertical, 3 for the E/W cor-

rection, 2 for the dynamic horizontal phase control,

2 for the vertical and horizontal Moiré options, 3 for

the horizontal and the vertical dynamic focus and 1

for the B+ reference adjustment.

18 bits are also dedicated to several controls (ON/

OFF, Horizontal Forced Frequency, Sync Priority,

Detection Refresh and XRAY reset).

1.4 Read Mode

During the read mode the second byte transmits

the reply information.

The reply byte contains the horizontal and vertical

lock/unlock status, the XRAY activation status,

and the horizontal and vertical polarity detection. It

also contains the sync detection status which is

used by the MCU to assign the sync priority. A

stop condition always stops all the activities of the

bus decoder and switches to high impedance both

the data and clock line (SDA and SCL).

See I

2C Bus Address Table.

1.5 Sync Processor

The internal sync processor allows the STV6886

to accept:

– separated horizontal & vertical TTL-compatible

sync signal

– composite horizontal & vertical TTL-compatible

sync signal

1.6 Sync Identification Status

The MCU can read (address read mode: 8D) the

status register via the I2C bus, and then select the

sync priority depending on this status.

Among other data this register indicates the pres-

ence of sync pulses on H/HVIN, VSYNCIN and

(when 12 V is supplied) whether a Vext has been

extracted from H/HVIN. Both horizontal and verti-

cal sync are detected even if only 5 V is supplied.

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