R8C2A datasheet(32/609 Pages) RENESAS

32 / 609 page

R8C/2A Group, R8C/2B Group

1. Overview

Rev.2.00

Nov 26, 2007

Page 12 of 580

REJ09B0324-0200

Figure 1.5

64-pin FLGA Package Pin Assignment (Top Perspective View)

P2_7/

TRDIOD1

P2_6/

TRDIOC1

P2_3/

TRDIOD0

P1_7/TRAIO/

INT

P1_6/CLK0

P8_5/

TRFO12

P4_5/INT0

P6_7/INT3/

RXD1

P4_6/XIN

P2_2/

TRDIOC0

P2_0/TRDIOA0/

TRDCLK

P1_4/TXD0

P6_6/INT2/

TXD1

VSS/AVSS

P2_4/

TRDIOA1

P2_1/

TRDIOB0

P1_5/RXD0/

(TRAIO)/(INT1)(2)

P8_1/

TRFO01

P4_4/XCOUT

P4_3/XCIN P3_5/SCL/

SSCK

P6_2

P6_3/TXD2

P1_3/KI3/

AN11

MODE

P3_7/SSO

P0_4/AN3

P6_1

P0_5/AN2/

CLK1

P3_1/TRBO

P3_4/SDA/

SCS

P0_0/AN7

P5_2/

TRCIOB

VREF

P3_0/TRAO P6_5/CLK2/

(CLK1)(2)

P0_1/AN6

P5_0/

TRCCLK

P0_6/AN1/

DA0

P6_0/TREO

P0_2/AN5

P5_4/

TRCIOD

VCC/AVCC

P4_7/

XOUT(1)

RESET P8_3/

TRFO10/TRFI

P6_4/RXD2

R5F212A7

SNLG

JAPAN

Pin assignments (top view)

Package: PTLG0064JA-A (64F0G)

NOTES:

1. P4_7 is an input-only port.

2. Can be assigned to the pin in parentheses by a

program.

P3_3/SSI

P0_3/AN4

P1_0/KI0/

AN8

P0_7/AN0/

DA1

P1_1/KI1/

AN9

P5_3/

TRCIOC

P3_6/

(INT1)(2)

P2_5/

TRDIOB1

P3_2/

(INT2)(2)

VCC/AVCC

P1_2/KI2/

AN10

VSS/AVSS

P8_2/

TRFO02

P8_4/

TRFO11

P5_1/TRCIOA/

TRCTRG

P8_6

P8_0/

TRFO00

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