HD6432138SW datasheet(517/1061 Pages) RENESAS

517 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 463 of 1004

REJ09B0301-0400

16.2.2

Slave Address Register (SAR)

Bit

Initial value

Read/Write

SVA6

R/W

SVA5

R/W

SVA4

R/W

SVA3

R/W

SVA2

R/W

SVA1

R/W

SVA0

R/W

SAR is an 8-bit readable/writable register that stores the slave address and selects the

communication format. When the chip is in slave mode (and the addressing format is selected), if

the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,

the chip operates as the slave device specified by the master device. SAR is assigned to the same

address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.

SAR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,

differing from the addresses of other slave devices connected to the I

2C bus.

Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in

DDCSWR to select the communication format.

• I2C bus format: addressing format with acknowledge bit

• Synchronous serial format: non-addressing format without acknowledge bit, for master mode

only

• Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit,

slave mode only, start/stop conditions not detected

The FS bit also specifies whether or not SAR slave address recognition is performed in slave

mode.

HD6432138SW Datasheet(PDF) 517 Page - Renesas Technology Corp