HD6432138SW datasheet(52/1061 Pages) RENESAS

52 / 1061 page

Rev. 4.00 Jun 06, 2006 page lii of liv

Table 24.3

Power-Down State Registers.................................................................................. 685

Table 24.4

MSTP Bits and Corresponding On-Chip Supporting Modules .............................. 694

Table 24.5

Oscillation Settling Time Settings.......................................................................... 696

Section 25 Electrical Characteristics

Table 25.1

Power Supply Voltage and Operating Range (1) (F-ZTAT Products) ................... 703

Table 25.1

Power Supply Voltage and Operating Range (2) (F-ZTAT A-Mask Products) ..... 704

Table 25.1

Power Supply Voltage and Operating Range (3) (Mask-ROM Products).............. 704

Table 25.1

Power Supply Voltage and Operating Range (4) (Mask-ROM Products).............. 705

Table 25.2

Absolute Maximum Ratings................................................................................... 706

Table 25.3

DC Characteristics (1) ............................................................................................ 707

Table 25.3

DC Characteristics (2) ............................................................................................ 710

Table 25.3

DC Characteristics (3) ............................................................................................ 713

Table 25.4

Permissible Output Currents .................................................................................. 716

Table 25.5

Bus Drive Characteristics ....................................................................................... 718

Table 25.6

Clock Timing ......................................................................................................... 719

Table 25.7

Control Signal Timing............................................................................................ 720

Table 25.8

Bus Timing............................................................................................................. 721

Table 25.9

Timing of On-Chip Supporting Modules (1).......................................................... 723

Table 25.9

Timing of On-Chip Supporting Modules (2).......................................................... 725

Table 25.10 I

2C Bus Timing....................................................................................................... 726

Table 25.11 A/D Conversion Characteristics

(AN7 to AN0 Input: 134/266-State Conversion) ................................................... 727

Table 25.12 A/D Conversion Characteristics

(CIN7 to CIN0 Input: 134/266-State Conversion) ................................................. 728

Table 25.13 D/A Conversion Characteristics ............................................................................. 729

Table 25.14 Flash Memory Characteristics (Programming/Erasing Operating Range) ............. 730

Table 25.15 Absolute Maximum Ratings................................................................................... 733

Table 25.16 DC Characteristics (1) ............................................................................................ 734

Table 25.16 DC Characteristics (2) ............................................................................................ 737

Table 25.16 DC Characteristics (3) ............................................................................................ 740

Table 25.17 Permissible Output Currents .................................................................................. 743

Table 25.18 Bus Drive Characteristics ....................................................................................... 744

Table 25.19 Clock Timing ......................................................................................................... 745

Table 25.20 Control Signal Timing............................................................................................ 746

Table 25.21 Bus Timing............................................................................................................. 747

Table 25.22 Timing of On-Chip Supporting Modules (1).......................................................... 749

Table 25.22 Timing of On-Chip Supporting Modules (2).......................................................... 751

Table 25.23 I

2C Bus Timing....................................................................................................... 752

Table 25.24 A/D Conversion Characteristics

(AN7 to AN0 Input: 134/266-State Conversion) ................................................... 753

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