HD6432351 datasheet(341/1025 Pages) RENESAS

341 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 307 of 988

REJ09B0330-0300

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Vector

Address

DTCE*

Priority

TGI3A (GR3A compare match/

input capture)

TPU

channel 3

H'0460

DTCEC5

High

TGI3B (GR3B compare match/

input capture)

H'0462

DTCEC4

TGI3C (GR3C compare match/

input capture)

H'0464

DTCEC3

TGI3D (GR3D compare match/

input capture)

H'0466

DTCEC2

TGI4A (GR4A compare match/

input capture)

TPU

channel 4

H'0470

DTCEC1

TGI4B (GR4B compare match/

input capture)

H'0472

DTCEC0

TGI5A (GR5A compare match/

input capture)

TPU

channel 5

H'0478

DTCED5

TGI5B (GR5B compare match/

input capture)

H'047A

DTCED4

DMTEND0A (DMAC transfer end 0) DMAC

H'0490

DTCEE7

DMTEND0B (DMAC transfer end 1)

H'0492

DTCEE6

DMTEND1A (DMAC transfer end 2)

H'0494

DTCEE5

DMTEND1B (DMAC transfer end 3)

H'0496

DTCEE4

RXI0 (reception complete 0)

H'04A2

DTCEE3

TXI0 (transmit data empty 0)

SCI

channel 0

H'04A4

DTCEE2

RXI1 (reception complete 1)

H'04AA

DTCEE1

TXI1 (transmit data empty 1)

SCI

channel 1

H'04AC

DTCEE0

Low

Note:

* DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

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