HD6432351 datasheet(347/1025 Pages) RENESAS

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HD6432351 Datasheet(PDF) 347 Page - Renesas Technology Corp

Part #	HD6432351

Description	16-Bit Single-Chip Microcomputer

PDF	1025 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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347 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 313 of 988

REJ09B0330-0300

8.3.8

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 8.9 shows the memory map for chain transfer.

Source

Destination

DTC vector

address

start address

CHNE = 1

CHNE = 0

Figure 8.9 Chain Transfer Memory Map

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

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