HD6432351 datasheet(350/1025 Pages) RENESAS

350 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 316 of 988

REJ09B0330-0300

Table 8.9

Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM

On-Chip I/O

Registers

External Devices

Bus width

Access states

Vector read

—

6+2m

3+m

read/write

—

Byte data read

3+m

Word data read

6+2m

3+m

Byte data write

3+m

Word data write

6+2m

3+m

Execution

status

Internal operation SM

The number of execution states is calculated from the formula below. Note that

Σ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

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