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HD6432351 Datasheet(PDF) 364 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 364 Page - Renesas Technology Corp |
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364 / 1025 page ![]() Section 9 I/O Ports Rev. 3.00 Sep 15, 2006 page 330 of 988 REJ09B0330-0300 Port 1 Data Direction Register (P1DDR) 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 0 P10DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W Bit Initial value R/W : : : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the PPG, TPU, and DMAC are initialized by a manual reset, the pin states are determined by the P1DDR and P1DR specifications. Port 1 Data Register (P1DR) 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 0 P10DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Bit Initial value R/W : : : P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. |
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