HD6432351 datasheet(434/1025 Pages) RENESAS

434 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 400 of 988

REJ09B0330-0300

9.13.2

Table 9.23 shows the port F register configuration.

Table 9.23 Port F Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port F data direction register

PFDDR

H'80/H'00*

H'FEBE

Port F data register

PFDR

R/W

H'00

H'FF6E

Port F register

PORTF

Undefined

H'FF5E

Notes: 1. Lower 16 bits of the address.

2. Initial value depends on the mode.

Port F Data Direction Register (PFDDR)

PF7DDR

PF6DDR

PF5DDR

PF4DDR

PF3DDR

PF0DDR

PF2DDR

PF1DDR

Bit

Modes 1, 2, 4 to 6

Initial value

R/W

Modes 3 and 7

Initial value

R/W

PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.

PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,

and 4 to 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in

software standby mode. The OPE bit in SBYCR is used to select whether the bus control output

pins retain their output state or become high-impedance when a transition is made to software

standby mode.

• Modes 1, 4, and 5 [H8S/2350]; modes 1, 2, and 4 to 6 [H8S/2351]

Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are

automatically designated as bus control outputs (

AS, RD, HWR, and LWR).

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