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HD6432351 Datasheet(PDF) 534 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 534 Page - Renesas Technology Corp |
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534 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 500 of 988 REJ09B0330-0300 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.54 shows the timing in this case. Input capture signal Write signal Address φ TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 10.54 Contention between TGR Write and Input Capture |
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