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HD6432351 Datasheet(PDF) 536 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 536 Page - Renesas Technology Corp |
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536 / 1025 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 3.00 Sep 15, 2006 page 502 of 988 REJ09B0330-0300 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clear signal TCNT input clock φ TCNT TGF Disabled TCFV H'FFFF H'0000 Figure 10.56 Contention between Overflow and Counter Clearing |
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