HD6432351 datasheet(570/1025 Pages) RENESAS

570 / 1025 page

Section 12 Watchdog Timer (WDT)

Rev. 3.00 Sep 15, 2006 page 536 of 988

REJ09B0330-0300

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources, obtained by dividing the system clock (

φ), for input to TCNT.

Description

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Clock

Overflow Period (when

φφφφ = 20 MHz)*

φ/2 (initial value)

25.6 µs

φ/64

819.2 µs

φ/128

1.6 ms

φ/512

6.6 ms

φ/2048

26.2 ms

φ/8192

104.9 ms

φ/32768

419.4 ms

φ/131072

1.68 s

Note:

* The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

12.2.3

Reset Control/Status Register (RSTCSR)

WOVF

R/(W)*

RSTE

R/W

RSTS

R/W

—

Note: * Can only be written with 0 for flag clearing.

Bit

Initial value

R/W

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

RSTCSR is initialized to H'1F by a reset signal from the

RES pin, but not by the WDT internal

reset signal caused by overflows.

Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For

details see section 12.2.4, Notes on Register Access.

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