HD6432351 datasheet(574/1025 Pages) RENESAS

574 / 1025 page

Section 12 Watchdog Timer (WDT)

Rev. 3.00 Sep 15, 2006 page 540 of 988

REJ09B0330-0300

12.3

Operation

12.3.1

Watchdog Timer Operation

To use the WDT as a watchdog timer, set the WT/

IT and TME bits to 1. Software must prevent

TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows

occurs. This ensures that TCNT does not overflow while the system is operating normally. If

TCNT overflows without being rewritten because of a system crash or other error, the

WDTOVF

signal is output. This is shown in figure 12.4. This

WDTOVF signal can be used to reset the

system. The

WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when

RSTE = 0.

If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2350

Group internally is generated at the same time as the

WDTOVF signal. This reset can be selected

as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The

internal reset signal is output for 518 states.

If a reset caused by a signal input to the

RES pin occurs at the same time as a reset caused by a

WDT overflow, the

RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.

TCNT count

H'00

Time

H'FF

WT/

IT = 1

TME = 1

H'00 written

to TCNT

WT/

IT = 1

TME = 1

H'00 written

to TCNT

132 states*2

518 states

WDTOVF signal

Internal reset signal*1

WT/

TME

Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.

2. 130 states when the RSTE bit is cleared to 0.

Overflow

WDTOVF and

internal reset are

generated

WOVF = 1

: Timer mode select bit

: Timer enable bit

Legend:

Figure 12.4 Watchdog Timer Operation

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