HD6432351 datasheet(578/1025 Pages) RENESAS

578 / 1025 page

Section 12 Watchdog Timer (WDT)

Rev. 3.00 Sep 15, 2006 page 544 of 988

REJ09B0330-0300

12.5.2

Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in

the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before

changing the value of bits CKS2 to CKS0.

12.5.3

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, errors could occur in the incrementation. Software must stop the watchdog timer (by

clearing the TME bit to 0) before switching the mode.

12.5.4

System Reset by

WDTOVF

WDTOVF Signal

If the

WDTOVF output signal is input to the RES pin of the H8S/2350 Group, the H8S/2350

Group will not be initialized correctly. Make sure that the

WDTOVF signal is not input logically

to the

RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown

in figure 12.9.

Reset input

Reset signal to entire system

H8S/2350 Group

RES

WDTOVF

Figure 12.9 Circuit for System Reset by

WDTOVF

WDTOVF Signal (Example)

12.5.5

Internal Reset in Watchdog Timer Mode

The H8S/2350 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0

during watchdog timer operation, but TCNT and TSCR of the WDT are reset.

TCNT, TCSR, and RSTCR cannot be written to while the

WDTOVF signal is low. Also note that

a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,

read TCSR after the

WDTOVF signal goes high, then write 0 to the WOVF flag.

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