HD6432351 datasheet(580/1025 Pages) RENESAS

580 / 1025 page

Section 13 Serial Communication Interface (SCI)

Rev. 3.00 Sep 15, 2006 page 546 of 988

REJ09B0330-0300

• Full-duplex communication capability

 The transmitter and receiver are mutually independent, enabling transmission and reception

to be executed simultaneously

 Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data

• On-chip baud rate generator allows any bit rate to be selected

• Choice of serial clock source: internal clock from baud rate generator or external clock from

SCK pin

• Four interrupt sources

 Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive

error — that can issue requests independently

 The transmit-data-empty interrupt and receive data full interrupts can activate the DMA

controller (DMAC) or data transfer controller (DTC) to execute data transfer

• Choice of LSB-first or MSB-first transfer

 Can be selected regardless of the communication mode* (except in the case of

asynchronous mode bit data)

• Module stop mode can be set

 As the initial setting, SCI operation is halted. Register access is enabled by exiting module

stop mode.

Note: * Descriptions in this section refer to LSB-first transfer.

HD6432351 Datasheet(PDF) 580 Page - Renesas Technology Corp