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HD6432351 Datasheet(PDF) 585 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 585 Page - Renesas Technology Corp |
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585 / 1025 page  Section 13 Serial Communication Interface (SCI) Rev. 3.00 Sep 15, 2006 page 551 of 988 REJ09B0330-0300 13.2.3 Transmit Shift Register (TSR) 7 — 6 — 5 — 4 — 3 — 0 — 2 — 1 — Bit R/W : : TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 13.2.4 Transmit Data Register (TDR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 0 1 R/W 2 1 R/W 1 1 R/W Bit Initial value R/W : : : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. |
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