HD6432351 datasheet(588/1025 Pages) RENESAS

588 / 1025 page

Section 13 Serial Communication Interface (SCI)

Rev. 3.00 Sep 15, 2006 page 554 of 988

REJ09B0330-0300

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit

character.

Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format

is selected, the PE bit and O/

E bit parity settings are invalid. The MP bit setting is only valid in

asynchronous mode; it is invalid in clocked synchronous mode.

For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor

Communication Function.

Bit 2

Description

Multiprocessor function disabled

(Initial value)

Multiprocessor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from

φ, φ/4, φ/16, and φ/64, according to the

setting of bits CKS1 and CKS0.

For the relation between the clock source, the bit rate register setting, and the baud rate, see

section 13.2.8, Bit Rate Register (BRR).

Bit 1

CKS1

Bit 0

CKS0

Description

φ clock

(Initial value)

φ/4 clock

φ/16 clock

φ/64 clock

HD6432351 Datasheet(PDF) 588 Page - Renesas Technology Corp