HD6432351 datasheet(875/1025 Pages) RENESAS

875 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 841 of 988

REJ09B0330-0300

IPRA—Interrupt Priority Register A

H'FEC4

Interrupt Controller

IPRB—Interrupt Priority Register B

H'FEC5

Interrupt Controller

IPRC—Interrupt Priority Register C

H'FEC6

Interrupt Controller

IPRD—Interrupt Priority Register D

H'FEC7

Interrupt Controller

IPRE—Interrupt Priority Register E

H'FEC8

Interrupt Controller

IPRF—Interrupt Priority Register F

H'FEC9

Interrupt Controller

IPRG—Interrupt Priority Register G

H'FECA

Interrupt Controller

IPRH—Interrupt Priority Register H

H'FECB

Interrupt Controller

IPRI—Interrupt Priority Register I

H'FECC

Interrupt Controller

IPRJ—Interrupt Priority Register J

H'FECD

Interrupt Controller

IPRK—Interrupt Priority Register K

H'FECE

Interrupt Controller

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Set priority (levels 7 to 0) for interrupt sources

IPRA

IPRB

IPRC

IPRD

IPRE

IPRF

IPRG

IPRH

IPRI

IPRJ

IPRK

Bits

IRQ0

IRQ2

IRQ3

IRQ6

IRQ7

WDT

—*

TPU channel 0

TPU channel 2

TPU channel 4

—*

DMAC

SCI channel 1

IRQ1

IRQ4

IRQ5

DTC

Refresh timer

A/D converter

TPU channel 1

TPU channel 3

TPU channel 5

—*

SCI channel 0

—*

6 to 4

2 to 0

Correspondence between Interrupt Sources and IPR Settings

Note: * Reserved bits. These bits cannot be modified and are

always read as 1.

Bit

Initial value

Read/Write

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