HD6432351 datasheet(879/1025 Pages) RENESAS

879 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 845 of 988

REJ09B0330-0300

BCRH—Bus Control Register H

H'FED4

Bus Controller

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

RMTS0

R/W

RMTS2

R/W

RMTS1

R/W

Bit

Initial value

Read/Write

Idle Cycle Insert 1

Idle cycle not inserted in case of successive external read cycles in different areas

Idle cycle inserted in case of successive external read cycles in different areas

Idle Cycle Insert 0

Idle cycle not inserted in case of successive external read and external write cycles

Idle cycle inserted in case of successive external read and external write cycles

Area 0 Burst ROM Enable

Area 0 is basic bus interface

Area 0 is burst ROM interface

Burst Cycle Select 1

Burst cycle comprises 1 state

Burst cycle comprises 2 states

Burst Cycle Select 0

Max. 4 words in burst access

Max. 8 words in burst access

RAM Type Select

RMTS2

RMTS1

—

RMTS0

—

Area 5 Area 4 Area 3 Area 2

Normal space

DRAM

space

Normal space

DRAM space

Normal

space

DRAM space

—

Note: When areas selected in DRAM space

are all 8-bit space, the PF2 pin can be

used as an I/O port,

BREQO, or WAIT.

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