HD6432351 datasheet(882/1025 Pages) RENESAS

882 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 848 of 988

REJ09B0330-0300

DRAMCR—DRAM Control Register

H'FED7

Bus Controller

RFSHE

R/W

RCW

R/W

RMODE

R/W

CMF

R/W

CMIE

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Refresh Control

Refresh control is not performed

Refresh control is performed

RAS-CAS Wait

Wait state insertion in CAS-before-RAS refreshing disabled

RAS falls in T

Rr cycle

Refresh Mode

DRAM interface: CAS-before-RAS refreshing used

Self-refreshing used

Compare Match Flag

Cleared by reading the CMF flag when CMF = 1, then

writing 0 to the CMF flag

[Clearing condition]

[Setting condition]

Set when RTCNT = RTCOR

Compare Match Interrupt Enable

Interrupt request (CMI) by CMF flag disabled

Interrupt request (CMI) by CMF flag enabled

Refresh Counter Clock Select

Count operation disabled

Count uses

φ/2

Count uses

φ/8

Count uses

φ/32

Count uses

φ/128

Count uses

φ/512

Count uses

φ/2048

Count uses

φ/4096

One wait state inserted in CAS-before-RAS refreshing

RAS falls in T

Rc1 cycle

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