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HD6432351 Datasheet(PDF) 901 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 901 Page - Renesas Technology Corp |
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901 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 867 of 988 REJ09B0330-0300 DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35 DTC 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 0 DTCE0 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W DTC Activation Enable Bit Initial value Read/Write : : : DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended 0 1 DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended Correspondence between Interrupt Sources and DTCER Bits Register 7 6 5 4 3 2 1 0 DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTCERB — ADI TGI0A TGI0B TGI0C TGI0D TGI1A TGI1B DTCERC TGI2A TGI2B TGI3A TGI3B TGI3C TGI3D TGI4A TGI4B DTCERD — — TGI5A TGI5B — — — — DTCERE DMTEND0A DMTEND0B DMTEND1A DMTEND1B RXI0 TXI0 RXI1 TXI1 DTCERF — — — — — — — — |
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