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HD6432351 Datasheet(PDF) 905 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 905 Page - Renesas Technology Corp |
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905 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 871 of 988 REJ09B0330-0300 SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator 7 PSTOP 0 R/W 6 — 0 R/W 5 — 0 — 4 — 0 — 3 — 0 — 0 SCK0 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 1 PSTOP Normal Operation φ output Fixed high High impedance High impedance Fixed high Fixed high φ Clock Output Control Bus Master Clock Select 0 1 0 1 0 1 0 1 0 1 0 1 — Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — φ output Fixed high Sleep Mode Bit Initial value Read/Write : : : Software Standby Mode Hardware Standby Mode |
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