HD6432351 datasheet(936/1025 Pages) RENESAS

936 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 902 of 988

REJ09B0330-0300

SCR1—Serial Control Register 1

H'FF82

SCI1

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Asynchronous

mode

Internal clock/SCK pin functions

as I/O port

Clock Enable

Transmit end interrupt (TEI) request disabled

Transmit end interrupt (TEI) request enabled

Transmit End Interrupt Enable

Multiprocessor interrupts disabled

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB = 1 data is received

Multiprocessor Interrupt Enable

Reception disabled

Reception enabled

Receive Enable

Transmission disabled

Transmission enabled

Transmit Enable

Receive data full interrupt (RXI) request and

receive error interrupt (ERI) request disabled

Receive Interrupt Enable

Transmit data empty interrupt (TXI) requests disabled

Transmit data empty interrupt (TXI) requests enabled

Transmit Interrupt Enable

Notes:

Bit

Initial value

Read/Write

Synchronous

mode

Internal clock/SCK pin functions

as serial clock output

Asynchronous

mode

Internal clock/SCK pin functions

as clock output*1

Synchronous

mode

Internal clock/SCK pin functions

as serial clock output

Asynchronous

mode

External clock/SCK pin functions

as clock input*2

Synchronous

mode

External clock/SCK pin functions

as serial clock input

Asynchronous

mode

External clock/SCK pin functions

as clock input*2

Synchronous

mode

External clock/SCK pin functions

as serial clock input

1. Outputs a clock of the same frequency as the bit rate.

2. Inputs a clock with a frequency 16 times the bit rate.

Multiprocessor interrupts enabled

Receive interrupt (RXI) requests, receive error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to 1

is received

Receive data full interrupt (RXI) request and

receive error interrupt (ERI) request enabled

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