HD6432351 datasheet(940/1025 Pages) RENESAS

940 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 906 of 988

REJ09B0330-0300

SSR1—Serial Status Register 1

H'FF84

Smart Card Interface 1

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Note: * Can only be written with 0 for flag clearing.

Transmit Data Register Empty

Receive Data Register Full

Overrun Error

Error Signal Status

Parity Error

Transmit End

Multiprocessor Bit

[Clearing condition]

When data with a 0 multiprocessor bit is received

Multiprocessor Bit Transfer

Data with a 0 multiprocessor bit is transmitted

Data with a 1 multiprocessor bit is transmitted

Bit

Initial value

Read/Write

[Setting conditions]

When data with a 1 multiprocessor bit is received

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC is activated by a TXI interrupt

and write data to TDR

[Setting conditions]

• On reset, or in standby mode or module stop mode

• When the TE bit in SCR is 0 and the ERS bit is 0

• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu

after a 1-byte serial character is sent when GM = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu

after a 1-byte serial character is sent when GM = 1

[Clearing condition]

When 0 is written to PER after reading PER = 1

[Setting condition]

When, in reception, the number of 1 bits in the receive data plus the parity bit

does not match the parity setting (even or odd) specified by the O/

E bit in SMR

[Clearing conditions]

• On reset, or in standby mode or module stop mode

• When 0 is written to ERS after reading ERS =1

[Setting conditions]

When the error signal is sampled at the low level

[Clearing condition]

When 0 is written to ORER after reading ORER = 1

[Setting condition]

When the next serial reception is completed while RDRF = 1

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR

[Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

Note: etu: Elementary Time Unit (the time taken to transmit one bit)

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.

HD6432351 Datasheet(PDF) 940 Page - Renesas Technology Corp

HD6432351 Datasheet(HTML) 940 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL