HD6432351 datasheet(951/1025 Pages) RENESAS

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Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 917 of 988

REJ09B0330-0300

TIOR0H—Timer I/O Control Register 0H

H'FFD2

TPU0

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA0

R/W

IOA2

R/W

IOA1

R/W

TGR0B I/O Control

TGR0A

is output

compare

TGR0A I/O Control

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and

φ/1 is used as the TCNT1 count clock, this setting is invalid

and input capture is not generated.

Bit

Initial value

Read/Write

Initial output is

0 output

TGR0A

is input

capture

Output disabled

Initial output is

1 output

Capture input

source is

TIOCA0 pin

Capture input

source is channel

1/count clock

Input capture at TCNT1 count-up/

count-down

TGR0B

is output

compare

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Initial output is

0 output

TGR0B

is input

capture

Output disabled

Initial output is

0 output

Capture input

source is

TIOCB0 pin

Capture input

source is channel

1/count clock

Input capture at TCNT1 count-up/

count-down*1

Legend: *: Don’t care

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