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HD6432351 Datasheet(PDF) 968 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 968 Page - Renesas Technology Corp |
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968 / 1025 page ![]() Appendix C I/O Port Block Diagrams Rev. 3.00 Sep 15, 2006 page 934 of 988 REJ09B0330-0300 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram R P1nDDR C QD Reset WDDR1 Reset WDR1 R P1nDR C QD P1n * RDR1 RPOR1 PPG module DMA controller TPU module Pulse output enable DMA transfer acknowledge enable Pulse output DMA transfer acknowledge Output compare output/ PWM output enable Output compare output/ PWM output Input capture input WDDR1 WDR1 RDR1 RPOR1 Notes: n = 0 or 1 * Priority order: Output compare output/PWM output > DMA transfer acknowledge output > pulse output > DR output Legend: : Write to P1DDR : Write to P1DR : Read P1DR : Read port 1 Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) |
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