HD6432351 datasheet(170/1025 Pages) RENESAS

170 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 136 of 988

REJ09B0330-0300

6.2.6

Memory Control Register (MCR)

TPC

R/W

RCDM

R/W

CW2

R/W

MXC1

R/W

RLW0

R/W

MXC0

R/W

RLW1

R/W

Bit

Initial value

R/W

MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number

of precharge cycles, access mode, address multiplexing shift size, and the number of wait states

inserted during refreshing, when areas 2 to 5 are designated as DRAM interface.

MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized

by a manual reset or in software standby mode.

Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be

used when areas 2 to 5 designated as DRAM space are accessed.

Bit 7

TPC

Description

1-state precharge cycle is inserted

(Initial value)

2-state precharge cycle is inserted

Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5

designated as DRAM space. DRAM space burst access is performed in fast page mode.

Bit 6

Description

Burst disabled (always full access)

(Initial value)

For DRAM space access, access in fast page mode

Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access

to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the

RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode).

RAS down mode cannot be used with the 2-CAS method. When selecting RAS down mode, set

the BE bit to 1.

HD6432351 Datasheet(PDF) 170 Page - Renesas Technology Corp

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