HD6432351 datasheet(225/1025 Pages) RENESAS

225 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 191 of 988

REJ09B0330-0300

6.11

Bus Arbitration

6.11.1

Overview

The H8S/2350 Group has a bus arbiter that arbitrates bus master operations.

There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations

when they have possession of the bus. Each bus master requests the bus by means of a bus request

signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by

means of a bus request acknowledge signal. The selected bus master then takes possession of the

bus and begins its operation.

6.11.2

Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

(High)

DMAC

DTC

CPU

(Low)

An internal bus access by an internal bus master, external bus release, and refreshing, can be

executed in parallel.

In the event of simultaneous external bus release request, refresh request, and internal bus master

external access request generation, the order of priority is as follows:

(High) Refresh > External bus release (Low)

(High) External bus release > Internal bus master external access (Low)

As a refresh and an external access by an internal bus master can be executed simultaneously,

there is no relative order of priority for these two operations.

HD6432351 Datasheet(PDF) 225 Page - Renesas Technology Corp