HD6432351 datasheet(229/1025 Pages) RENESAS

229 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 195 of 988

REJ09B0330-0300

Section 7 DMA Controller (DMAC)

7.1

Overview

The H8S/2350 Group has a built-in DMA controller (DMAC) which can carry out data transfer on

up to 4 channels.

7.1.1

Features

The features of the DMAC are listed below.

• Choice of short address mode or full address mode

Short address mode:

 Maximum of 4 channels can be used

 Choice of dual address mode or single address mode

 In dual address mode, one of the two addresses, transfer source and transfer destination, is

specified as 24 bits and the other as16 bits

 In single address mode, transfer source or transfer destination address only is specified as

24 bits

 In single address mode, transfer can be performed in one bus cycle

 Choice of sequential mode, idle mode, or repeat mode for dual address mode and single

address mode

Full address mode:

 Maximum of 2 channels can be used

 Transfer source and transfer destination address specified as 24 bits

 Choice of normal mode or block transfer mode

• 16-Mbyte address space can be specified directly

• Byte or word can be set as the transfer unit

• Activation sources: internal interrupt, external request, auto-request (depending on transfer

mode)

 Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts

 Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception

complete interrupt

 A/D converter conversion end interrupt

 External request

 Auto-request

HD6432351 Datasheet(PDF) 229 Page - Renesas Technology Corp