HD6432351 datasheet(231/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 197 of 988

REJ09B0330-0300

7.1.3

Overview of Functions

Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode,

respectively.

Table 7.1 (1) Overview of DMAC Functions (Short Address Mode)

Address Register Bit Length

Transfer Mode

Transfer Source

Source

Destination

Dual address mode

• Sequential mode

 1-byte or 1-word transfer

executed for one transfer request

 Memory address

incremented/decremented by 1

or 2

 1 to 65536 transfers

• Idle mode

 1-byte or 1-word transfer

executed for one transfer request

 Memory address fixed

 1 to 65536 transfers

• Repeat mode

 1-byte or 1-word transfer

executed for one transfer request

 Memory address incremented/

decremented by 1 or 2

 After specified number of

transfers (1 to 256), initial state is

restored and operation continues

• TPU channel 0

to 5 compare

match/input

capture A

interrupt

• SCI transmission

complete

interrupt

• SCI reception

complete

interrupt

• A/D converter

conversion end

interrupt

• External request

24/16

16/24

Single address mode

• 1-byte or 1-word transfer executed

for one transfer request

• Transfer in 1 bus cycle using DACK

pin in place of address specifying I/O

• Specifiable for sequential, idle, and

repeat modes

• External request

24/

DACK

DACK/24

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