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HD6432351 Datasheet(PDF) 235 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 235 Page - Renesas Technology Corp |
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235 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 201 of 988 REJ09B0330-0300 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.4 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 Description 0 Short address mode specified (channels A and B operate independently) MAR0A Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B 1 Full address mode specified (channels A and B operate in combination) MAR0A Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B |
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