HD6432351 datasheet(276/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 242 of 988

REJ09B0330-0300

7.5.4

Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to

0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer

request, and this is executed the number of times specified in ETCR. On completion of the

specified number of transfers, MAR and ETCRL are automatically restored to their original

settings and operation continues.

One address is specified by MAR, and the other by IOAR. The transfer direction can be specified

by the DTDIR bit in DMACR.

Table 7.8 summarizes register functions in repeat mode.

Table 7.8

Function

DTDIR = 0

DTDIR = 1

Initial Setting

Operation

MAR

Source

address

Destination

address

Start address

of transfer

destination or

transfer source

Incremented/

decremented every

transfer. Initial

setting is restored

when value reaches

H'0000

IOAR

H'FF

Destination

address

Source

address

Start address

of transfer

source or

transfer

destination

Fixed

ETCRH

ETCRL

Holds number of

transfers

Transfer counter

Number of

transfers

Number of

transfers

Fixed

Decremented every

transfer. Loaded

with ETCRH value

when count reaches

H'00

Legend:

MAR:

Memory address register

IOAR: I/O address register

ETCR: Transfer count register

DTDIR: Data transfer direction bit

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