HD6432351 datasheet(277/1025 Pages) RENESAS

277 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 243 of 988

REJ09B0330-0300

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred.

IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of

H'FF.

The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of

transfers, when H'00 is set in both ETCRH and ETCRL, is 256.

In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number

of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value

reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is

restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR

restoration operation is as shown below.

MAR = MAR – (–1)DTID · 2DTSZ · ETCRH

The same value should be set in ETCRH and ETCRL.

In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation,

therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU

or DTC.

By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the

transfer after that terminated when the DTE bit was cleared.

HD6432351 Datasheet(PDF) 277 Page - Renesas Technology Corp