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HD6432351 Datasheet(PDF) 284 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 284 Page - Renesas Technology Corp |
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284 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 250 of 988 REJ09B0330-0300 Figure 7.11 illustrates operation in normal mode. Address TA Address BA Transfer Address TB Notes: Address Address Address Address Where : Address BB = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA TA TB BA BB LA LB N Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. |
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