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HD6432351 Datasheet(PDF) 286 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 286 Page - Renesas Technology Corp |
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286 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 252 of 988 REJ09B0330-0300 7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.11 summarizes register functions in block transfer mode. Table 7.11 Register Functions in Block Transfer Mode Register Function Initial Setting Operation 23 0 MARA Source address register Start address of transfer source Incremented/decremented every transfer, or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented/decremented every transfer, or fixed 0 ETCRAH 7 0 ETCRAL 7 Holds block size Block size counter Block size Block size Fixed Decremented every transfer; ETCRH value copied when count reaches H'00 15 0 ETCRB Block transfer counter Number of block transfers Decremented every block transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A ETCRB: Transfer count register B |
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