H8SX1663 datasheet(194/1158 Pages) RENESAS

194 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 142 of 1102

REJ09B0294-0100

6.2.4

Read Strobe Timing Control Register (RDNCR)

RDNCR selects the negation timing of the read strobe signal (

RD) when reading the external

address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.

Bit

Bit Name

Initial Value

R/W

RDN7

R/W

RDN6

R/W

RDN5

R/W

RDN4

R/W

RDN3

R/W

RDN2

R/W

RDN1

R/W

RDN0

R/W

Bit

Bit Name

Initial Value

R/W



Bit

Bit Name

Initial

Value

R/W

Description

RDN7

RDN6

RDN5

RDN4

RDN3

RDN2

RDN1

RDN0

R/W

Read Strobe Timing Control

RDN7 to RDN0 set the negation timing of the read

strobe in a corresponding area read access.

As shown in figure 6.2, the read strobe for an area for

which the RDNn bit is set to 1 is negated one half-

cycle earlier than that for an area for which the RDNn

bit is cleared to 0. The read data setup and hold time

are also given one half-cycle earlier.

0: In an area n read access, the

RD signal is negated

at the end of the read cycle

1: In an area n read access, the

RD signal is negated

one half-cycle before the end of the read cycle

(n = 7 to 0)

7 to 0



All 0

Reserved

These are read-only bits and cannot be modified.

Notes: 1. In an external address space which is specified as byte control SRAM interface, the

RDNCR setting is ignored and the same operation when RDNn = 1 is performed.

2. In an external address space which is specified as burst ROM interface, the RDNCR

setting is ignored during CPU read accesses and the same operation when RDNn = 0 is

performed.

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